1. Field of the Invention
The present invention relates to code generation and, more specifically, to generating optimized code.
2. Background Information
Engineers and scientists often use computer-based, high-level development tools or environments to perform algorithm development, data visualization, simulation, and model design, among other tasks. Exemplary high-level development tools include the MATLAB® and Simulink® technical computing environments from The MathWorks, Inc. of Natick, Mass. With the Simulink® technical computing environment, a user creates a graphical model by dragging and dropping blocks from a library browser onto a graphical editor, and connecting them with lines that establish mathematical relationships and/or signals between the blocks. Stateflow® modeling environment is an extension to is the Simulink® technical computing environment that allows users to specify state machines and flow charts. A Stateflow chart may be created by dragging states, junctions and functions from a graphical palette into a drawing window. The user can then create transitions and flow by connecting states and junctions together.
Other add-on products or tools exist for generating code from Simulink models, MATLAB files and/or functions, often referred to as M-files, and/or Stateflow charts. Specifically, a Simulink Hardware Description Language (HDL) Coder™ add-on product, also available from The MathWorks, Inc., generates HDL code based on Simulink models or Stateflow charts. The generated HDL code can be exported to synthesis and layout tools for hardware realization, such as Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Complex Programmable Logic Devices (CPLDs), etc. With the release of the Simulink HDL Coder add-on product, the Simulink technical computing environment can now be used for electronic design automation.
With the Simulink HDL Coder add-on product, a user may create a code generation control file that is attached to a model. The control file allows the user to set code generation options, such as how HDL code is generated for selected sets of blocks within the model. In this way, the generated HDL code may be optimized for speed, chip area, latency, etc.